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WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 1 general description the WT6018 is a member of wt60xx microcontroller family. it is specially designed for digital controlled multi-sync monitor. it contains 8-bit cpu, 8k bytes rom, 288 bytes ram, 14 pwms, parallel i/o, sync processor, timer, ddc interface (slave mode i 2 c interface with ddc1), two 4-bit a/d convertors and watch-dog timer. features * 8-bit 6502 compatible cpu, 4mhz operating frequency * 8192 bytes rom, 288 bytes sram * 8mhz crystal oscillator * 14 channels 8-bit/62.5khz pwm outputs (8 open drain outputs & 6 cmos outputs) * sync signal processor with h+v separation, frequency calculation, h/v polarity detection/control * three free-running sync signal outputs for burn-in test (64khz/62.5hz, 48khz/75hz, 31khz/60hz) * self-test pattern generator generates cross hatch picture * provide half frequency input and output * ddc interface supports vesa ddc1/ddc2b standard * watch-dog timer (0.524 second) * maximum 25 programmable i/o pins * one 8-bit programmable timer * two 4-bit a/d converter * one external interrupt request * built-in low v dd voltage reset * +5v power supply pin assignment * i 2 c is a trademark of philips corporation. * ddc is a trademark of video electronics standard association (vesa). 41 42 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 da0 da1 da2 da3 da4 da5 da6 da7 gnd hsync osci osco pa0/da8 pa1/da9 pa2/da10 pa3/da11 pa4/da12 pa5/da13 pa6/vso pa7/hso pb0/hlfo pb1/hlfi pb2 pb3/pat pb4 pb5 pb6/irq pc0/ad0 pc1/ad1 pc2 pc3 pc4 pc5 pc6 pc7 scl/pd0 sda/pd1 vdd vsync reset 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 da0 da1 da2 da3 da4 da5 da6 da7 gnd hsync osci osco pa0/da8 pa1/da9 pa2/da10 pa3/da11 pa4/da12 pa5/da13 pa6/vso pa7/hso pb0/hlfo pb1/hlfi pb2 pb3/pat pb4 pb5 pb6/irq pc0/ad0 pc1/ad1 pc2 pc3 pc4 pc5 pc6 pc7 scl/pd0 sda/pd1 vdd vsync reset 42-pin sdip 40-pin pdip
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 2 pin description pin no. 40 42 pin name i/o descriptions 1 1 da2 o d/a converter 2. open-drain output. external applied voltage can up to 10v. 2 2 da1 o d/a converter 1. open-drain output. external applied voltage can up to 10v. 3 3 da0 o d/a converter 0. open-drain output. external applied voltage can up to 10v. 4 4 /reset i reset. active low. schmitt trigger input, internal pull high. 5 5 vdd power supply (+5v). 6 7 gnd ground (0v). 7 8 osco o oscillator output. connects a 8mhz crystal. 8 9 osci i oscillator input. connects a 8mhz crystal. 9 10 pb5 i/o i/o port b5. when it is an input pin, it has an internal pull-up resistor. when it is an output pin, the sink current is 5ma and the source current is 5ma. 10 11 pb4 i/o i/o port b4. same as pb5. 11 12 pb3/pat i/o i/o port b3 or self-test pattern output . when as an i/o port, it is same as pb5. when it is configured to test pattern output, a vedio signal is output. 12 13 pb2 i/o i/o port b2 . same as pb5. 13 14 pb1/hlfi i/o i/o port b1 or half frequency input. 14 15 pb0/hlfo i/o i/o port b0 or half frequency output. 15 16 pb6/irq i/o i/o port b6 or interrupt request . when as interrupt request input, it has an internal pull high resistor. when as an i/o port, it is same as pb5. 16 17 pc7 i/o i/o port c7 . when it is an input pin, it has an internal pull-up resistor. when it is an output pin, the sink current is 10ma and the source current is 5ma. 17 18 pc6 i/o i/o port c6 . same as pc7. 18 19 pc5 i/o i/o port c5 . same as pc7. 19 20 pc4 i/o i/o port c4 . same as pc7. 20 21 pc3 i/o i/o port c3 . same as pc7. 21 22 pc2 i/o i/o port c2 . same as pc7. 22 23 pc1/ad1 i/o i/o port c1 or a/d converter input 0. 23 24 pc0/ad0 i/o i/o port c0 or a/d converter input 1. 24 25 sda /pd1 i/o ddc serial data or i/o port d1 . when it is a ddc interface pin, it is an open- drain output. when as an i/o port, it is same as port b. 25 26 scl /pd0 i/o ddc serial clock or i/o port d0. when it is a ddc interface pin, it is an open- drain output. when as an i/o port, it is same as port b. 26 27 pa0/da8 i/o i/o port a0 or d/a converter 8 . this pin can be the output of d/a converter 8 (source/sink = 5ma) or an i/o pin (source = -100ua, sink = 5ma). 27 28 pa1/da9 i/o i/o port a1 or d/a converter 9 . same as pa0/da8. 28 29 pa2/da10 i/o i/o port a2 or d/a converter 10 . same as pa0/da8. 29 30 pa3/da11 i/o i/o port a3 or d/a converter 11 . same as pa0/da8. 30 31 pa4/da12 i/o i/o port a4 or d/a converter 12 . same as pa0/da8. 31 32 pa5/da13 i/o i/o port a5 or d/a converter 13 . same as pa0/da8. 32 33 pa6/vso i/o i/o port a6 / vsync out . this pin can be the output of vsync or an i/o pin. when as an i/o pin, it is same as pa0. 33 34 pa7/hso i/o i/o port a7 / hsync out . this pin can be the output of hsync or an i/o pin. when as an i/o pin, it is same as pa0. 34 35 da7 o d/a converter 7. open-drain output. external applied voltage can up to 10v. 35 36 da6 o d/a converter 6. open-drain output. external applied voltage can up to 10v. 36 38 da5 o d/a converter 5. open-drain output. external applied voltage can up to 10v. 37 39 da4 o d/a converter 4. open-drain output. external applied voltage can up to 10v. 38 40 da3 o d/a converter 3. open-drain output. external applied voltage can up to 10v. 39 41 hsync i hsync input . schmitt trigger input. 40 42 vsync i vsync input . schmitt trigger input.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 3 functional description cpu the cpu core is 6502 compatible, operating frequency is 4mhz. address bus is 16-bit and data bus is 8-bit. the non-maskable interrupt (/nmi) of 6502 is changed to maskable interrupt and is defined as the int0. the interrupt request (/irq) of 6502 is defined as the int1. default stack pointer is 01ffh. please refer the 6502 reference menu for more detail. rom 8192 bytes maskable rom is provided for program codes. address is located from e000h to ffffh. the following addresses are reserved for special purpose : fffah (low byte) and fffbh (high byte ) : int0 interrupt vector. fffch (low byte) and fffdh (high byte ) : program reset vector. fffeh (low byte) and ffffh (high byte ) : int1 interrupt vector. ram built-in 288 bytes sram, address is located from 0080h to 019fh. because the initial stack pointer is 01ffh, so program must set proper stack pointer when program starts. a recommended value is 019fh. 0000h : 0020h registers 0021h : 007fh reserved 0080h : 019fh ram 01a0h : dfffh reserved e000h : : : ffffh rom low vdd voltage reset a vdd voltage detector is built inside the chip. when vdd is below 4.0 volts, the whole chip will be reset just like power-on-reset. note that the 4.0 volts varies with temperature and process. please refer the electrical characteristics.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 4 pwm d/a converter the WT6018 provides 14 pwm d/a converters. da0 to da7 are open-drain outputs and external applied voltage on these pins can be up to 10 volts. da8 to da13 are 5 volts push-pull cmos outputs and are shared with i/o port pa0 to pa5. all d/a converters are 62.5khz frequency with 8-bit resolution. each d/a converter is controlled by the corresponding register (reg#00h to reg#0dh), the duty cycle can be programmed from 1/256 (data = 01h) to 255/256 (data = ffh). duty cycle = 1/256 62.5ns duty cycle = 2/256 125ns 62.5ns duty cycle = 255/256 1/62.5khz=16us to program the pwm d/a converters, write the corresponding registers ( reg#00h to reg#0dh). address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000h r/w 80h da0 7 da0 6 da0 5 da0 4 da0 3 da0 2 da0 1 da0 0 0001h r/w 80h da1 7 da1 6 da1 5 da1 4 da1 3 da1 2 da1 1 da1 0 0002h r/w 80h da2 7 da2 6 da2 5 da2 4 da2 3 da2 2 da2 1 da2 0 0003h r/w 80h da3 7 da3 6 da3 5 da3 4 da3 3 da3 2 da3 1 da3 0 0004h r/w 80h da4 7 da4 6 da4 5 da4 4 da4 3 da4 2 da4 1 da4 0 0005h r/w 80h da5 7 da5 6 da5 5 da5 4 da5 3 da5 2 da5 1 da5 0 0006h r/w 80h da6 7 da6 6 da6 5 da6 4 da6 3 da6 2 da6 1 da6 0 0007h r/w 80h da7 7 da7 6 da7 5 da7 4 da7 3 da7 2 da7 1 da7 0 0008h r/w 80h da8 7 da8 6 da8 5 da8 4 da8 3 da8 2 da8 1 da8 0 0009h r/w 80h da9 7 da9 6 da9 5 da9 4 da9 3 da9 2 da9 1 da9 0 000ah r/w 80h da10 7 da10 6 da10 5 da10 4 da10 3 da10 2 da10 1 da10 0 000bh r/w 80h da11 7 da11 6 da11 5 da11 4 da11 3 da11 2 da11 1 da11 0 000ch r/w 80h da12 7 da12 6 da12 5 da12 4 da12 3 da12 2 da12 1 da12 0 000dh r/w 80h da13 7 da13 6 da13 5 da13 4 da13 3 da13 2 da13 1 da13 0 bit name bit value dax7-dax0 01h : 1/256 duty cycle 02h : 2/256 duty cycle 03h : 3/256 duty cycle : ffh : 255/256 duty cycle ** do not write 00h to the pwm registers. this will cause unstable output on the corresponding pin.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 5 i/o ports port_ a : pin pa0/da8 - general purpose i/o shared with da8 output. pin pa1/da9 - general purpose i/o shared with da9 output. pin pa2/da10 - general purpose i/o shared with da10 output. pi n pa3/da11 - general purpose i/o shared with da11 output. pin pa4/da12 - general purpose i/o shared with da12 output. pin pa5/da13 - general purpose i/o shared with da13 output. pin pa6/vso - general purpose i/o shared with vsync output. pin pa7/h so - general purpose i/o shared with hsync output. port_a is controlled by reg#10h & reg#11h. in reg#10h, each corresponding bit enables hsync output, vsync output or d/a converter output when it is "1". if the corresponding bit is "0", the output level is decided by reg#11h. in reg#11h, if the i/o corresponding bit (pan) is "0", the output is low level (i ol =5ma). if pan bit is "1", the output is high level (i oh = -100ua) and can be used as an input. address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0010h w 00h eho evo eda13 eda12 eda11 eda10 eda9 eda8 0011h w ffh pa7w pa6w pa5w pa4w pa3w pa2w pa1w pa0w 0011h r -- pa7r pa6r pa5r pa4r pa3r pa2r pa1r pa0r bit name bit value = ? 1 ? bit value = ? 0 ? eho enable pa7 as hsync output. pa7 as general purpose i/o. evo enable pa6 as vsync output. pa6 as general purpose i/o. eda13 enable pa5 as da13 output. pa5 as general purpose i/o. eda12 enable pa4 as da12 output. pa4 as general purpose i/o. eda11 enable pa3 as da11 output. pa3 as general purpose i/o. eda10 enable pa2 as da10 output. pa2 as general purpose i/o. eda9 enable pa1 as da9 output. pa1 as general purpose i/o. eda8 enable pa0 as da8 output. pa0 as general purpose i/o. pa7w - pa0w outputs high level (i oh = -100ua). outputs low level (i ol = 5ma). pa7r- pa0r pin is high level. pin is low level. * if the program wants to force vsync output (vso pin) in low state, write "0" to pa6 bit first, then write "0" to evo bit. this is used to prevent high frequency output on vso pin when the vsync frequency is increased to read edid data in ddc1 mode. edax dax panw panr pin pan 5ma 5ma 100ua
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 6 port_ b : pin pb0/hlfo - general purpose i/o pins shared with half frequency output. pin pb1/hlfi - general purpose i/o pins shared with half frequency input. pin pb2 - general purpose i/o pins. pin pb3/pat - general purpose i/o pin shared with self-test pattern output. pin pb4 to pb5 - general purpose i/o pins. pin pb6/irqb - general purpose i/o pin shared with interrupt request input. the source/sink current of port_b is 5ma when a s an output. when it is input, an internal pull high resistor is connected. address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0012h w 00h 0 pb6oe pb5oe pb4oe pb3oe pb2oe pb1oe pb0oe 0013h w ffh 1 pb6w pb5w pb4w pb3w pb2w pb1w pb0w 0013h r -- -- pb6r pb5r pb4r pb3r pb2r pb1r pb0r bit name bit value = ? 1 ? bit value = ? 0 ? pb6oe - pb0oe output enable. output disable (internal pull-up). pb6w - pb0w outputs high level (i oh = -5ma). outputs low level (i ol = 5ma). pb6r- pb0r pin is high level. pin is low level. * if enhalf bit in reg#17h is ? 1 ? , the pb0 and pb1 pins are for half frequency function. * if enpat bit in reg#16h is ? 1 ? , the pb3 pin becomes self-test pattern output. * if ien_x bit in reg#1ah is ? 1 ? and pb6oe bit is "0", the pb6 pin becomes interrupt request input. structure of i/o port b pbnoe pbnw pbnr 5ma 5ma 100ua pin pb0 to pb6
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 7 port_ c : pin pc0 - general purpose i/o pin shared with 4-bit a/d converter 0 input. pin pc1 - general purpose i/o pin shared with 4-bit a/d converter 1 input pin pc2 to pc7 - general purpose i/o pins. the reg#14h defines the i/o direction and the reg#15h controls the output level. the structure of port_c is same as the port_b except the sink current is 10ma. when pc0 and pc1 are programmed as the a/d converter inputs, the pull high transistor is disconnected. address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0014h w 00h pc7oe pc6oe pc5oe pc4oe pc3oe pc2oe pc1oe pc0oe 0015h w ffh pc7w pc6w pc5w pc4w pc3w pc2w pc1w pc0w 0015h r -- pc7r pc6r pc5r pc4r pc3r pc2r pc1r pc0r bit name bit value = ? 1 ? bit value = ? 0 ? pc7oe - pc0oe output enable. output disable (internal pull-up). pc7w - pc0w outputs high level (i oh = -5ma). outputs low level (i ol = 10ma). pc7r - pc0r pin is high level. pin is low level. port_ d : pin scl/pd0 - general purpose i/o pin shared with ddc interface serial clock. pin sda/pd1 - general purpose i/o pin shared with ddc interface serial data. the structure of these two pins are same as the pb4 and pb5. default is ddc interface and can be changed to i/o port d by setting enpd bit. address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000fh w 00h -- -- -- enpd pd1oe pd0oe pd1w pd0w 000fh r -- -- -- -- -- -- -- pd1r pd0r bit name bit value = ? 1 ? bit value = ? 0 ? enpd enable i/o port_d. ddc interface.(open drain) pd1oe - pd0oe output enable. output disable (internal pull-up). pd1w - pd0w outputs high level (i oh = -5ma). outputs low level (i ol = 5ma). pd1r- pd0r pin is high level. pin is low level. * if program wants to read current status on the i/o pins (any i/o port), do not set output enable bit to ? 0 ? . because the registers for reading i/o are always indicating the current state on the i/o pins, set output enable bit to ? 0 ? will change the level on the i/o pin. please reference the i/o pin structure.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 8 sync processor the sync processor can : (1) separate the composite sync signal; (2) calculate hsync and vsync frequencies; (3) detect polarities of hsync and vsync inputs; (4) control the output polarities of hso and vso pins. (5) generate free-running horizontal and vertical sync signals for burn-in test; (6) generate self-test pattern signal. composite sync signal separation the composite sync signal comes from hsync pin and is separated by the sync separator. the operations of sync separator are: - detect the polarity and convert composite sync signal to positive polarity. - extract vsync pulse width less than 8us will be filtered, but the vsync will be widened about 8us. - count the pulses during the separated vsync is low and save the counter value (n h ). - bypass the composite sync pulses before the counter equals to n h. - start inserting hsync pulses after the counter equals to n h until the separated vsync is low. - the period of inserted hsync is decided by the last two bypassed hsync. - the pulse width of the inserted hsync is 2us. to decide whether the hsync input is a composite sync signal or not, program should check the frequency of vsync first (reset h+v bit to ? 0 ? ). if the vsync frequency is lower than 15.25hz (ovf2=1), set h+v bit to ? 1 ? and check vsync frequency again. if vsync still has no frequency, that is power saving condition, program should reset h+v bit. if it has a valid frequency, the hsync input is composite signal. separated vsync positive h+v separated hsync bypass insert hsync h/v sync generator sync separator hsync vsync h/v freq. counter h polarity detect hso vso mux mux mux mux test pattern generator mux pb3 pb3/pat h v v polarity detect & control h polarity control self h+v h+v
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 9 frequency calculation horizontal frequency and vertical frequencies calculation are done by using one 10-bit up counter. after power is on, the sync processor calculates the vertical frequency first (h/v bit ="0"). a 31.25khz clock counts the time interval between two vsync pulses, then sets the frdy bit and generates an int1 interrupt (if ien_s bit is "1"). the software can either use interrupt or polling the frdy bit to read the correct vertical frequency. after reading the reg#16h, the frdy bit is cleared to "0", counter is reset and h/v bit is set. the sync processor starts to count horizontal frequency. the horizontal frequency calculation is done by counting the hsync pulses in 8.192 ms. like the vertical frequency, the horizontal frequency can be read when the frdy bit is set or int1 occurs. after reading the reg#16h, the frdy, int_s and h/v bits are cleared. the sync processor starts to calculate the vertical frequency again, and so on. the relationships between counter value and frequency are : hfreq = (counter value x 122.07) hz vfreq = ( 31250 / counter value ) hz the frequency range : hfreq range : 122.07 hz to 124.8 khz ; resolution : 122.07hz vfreq range : 30.5 hz to 31.25 khz if counter overflowed, the ovf1 bit will be set to "1". the counter keeps on counting until it overflowed again. the ovf2 bit and frdy bit will be set when counter overflowed twice. this is designed for finding the vertical frequency bellows 15.25hz. the program should check reg#17h before reading reg#16h. polarity detect/control the polarities of hsync and vsync are automatically detected and are shown in the h_pol and v_pol bits. the polarities of hso and vso are controlled by the hop and vop bits. for example, set hop bit to ? 1 ? , the hso pin always outputs positive horizontal sync signal, whatever the hsync input ? s polarity is. free-running sync signal the self-generated sync signals are output from hso and vso pins if self bit is ? 1 ? . three kinds of frequencies are provided : (1) hfreq = 8mhz/125 = 64.0khz, vfreq = hfreq/1024 = 62.5hz. (2) hfreq = 8mhz/167 = 47.9khz, vfreq = hfreq/640 = 74.9hz. (3) hfreq = 8mhz/257 = 31.1khz, vfreq = hfreq/512 = 60.8hz . the output polarities are controlled by the hop and vop bits. the pulse width of hso is 2us and vso is four hso cycles. the timing relationship is shown in the following : 2us hso vso
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 10 test pattern generation a self-test pattern signal comes out from pin pb3/pat. it can generate a cross hatch picture, a inverted cross hatch picture, a white picture or a black picture. the test pattern signal is generated when self and enpat are both set to ? 1 ? . this vedio signal will synchronize to the free-running hsync and vsync, no matter which frequency is chosen. the following diagram shows the timing relationship of cross hatch picture. hso vso t 1 t 2 t 3 31.1khz 60.8hz 6us 1us 62.5ns 47.9khz 74.9hz 5.125us 0.625us 62.5ns 64khz 62.5hz 3.625us 0.875us 62.5ns 8 x 8 cross hatch inverted 8 x 8 cross hatch white picture black picture t 1 t 1 t 2 t 2 t 3 hso pat
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 11 half frequency hlfo pin outputs same or half frequency from hlfi pin. the divide-by-2 operation is done on the falling edge of hlfi pin when half bit is set. polarity of hlfo is specified by hlfpo bit. r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0016h w -- 0 0 enpat pat1 pat0 self h64k h48k 0016h r -- f9 f8 f7 f6 f5 f4 f3 f2 0017h w -- -- -- enhlf half hlfpo h+v hop vop 0017h r 00h h/v -- h_pol v_pol ovf2 ovf1 f1 f0 bit name bit value = ? 1 ? bit value = ? 0 ? enpat pin pb3/pat outputs test pattern. pin pb3/pat is i/o port. pat1,pat0 if pat1=0, pat0=0, cross hatch picture. if pat1=0, pat0=1, white picture. if pat1=1, pat0=0, inverted cross hatch picture. if pat1=1, pat0=1, black picture. self hso and vso output free-running frequency. hso and vso output sync signals. h64k, h48k h64k= ? 1 ? ,h48k= ? 1 ? : burn-in frequency=47.9khz/74.9hz h64k= ? 0 ? ,h48k= ? 1 ? : burn-in frequency=47.9khz/74.9hz h64k= ? 1 ? ,h48k= ? 0 ? : burn-in frequency=64khz/62.5hz h64k= ? 0 ? ,h48k= ? 0 ? : burn-in frequency=31.1khz/60.8hz enhlf pin pb1/hlfi is frequency input. pin pb0/hlfo is half frequency output. pin pb1/hlfi and pb0/hlfo is i/o port. half hlfo outputs half frequency of hlfi. hlfo outputs same frequency of hlfi hlfpo hlfo is positive polarity. hlfo is negative polarity. h+v enable h+v separation function. this will select the sync signals come from the sync separator. disable h+v separation. hop hso pin is always positive polarity. hso pin is always negative polarity. vop vso pin is always positive polarity. vso pin is always negative polarity. h/v counter stores horizontal frequency. counter stores vertical frequency. h_pol hsync input is positive polarity. hsync input is negative polarity. v_pol vsync input is positive polarity. vsync input is negative polarity. ovf2, ovf1 ovf2= ? 1 ? ,ovf1= ? 0 ? : counter overflowed twice. ovf2= ? 0 ? ,ovf1= ? 1 ? : counter overflowed once. ovf2= ? 0 ? ,ovf1= ? 0 ? : no overflow. ovf2= ? 1 ? ,ovf1= ? 1 ? : no such condition. f9-f0 frequency counter value. (f9 is msb) (half=1) hlfo hlfi (hlfpo=0) (half=0) hlfo (hlfpo=1) (half=0) hlfo
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 12 ddc interface the ddc interface is a slave mode i 2 c interface with ddc1 function. it is fully compatible with veas ddc1/2b standard. the functional block diagram is shown in the below. after power on or reset the ddc interface, it is in ddc1 state. the shift register shifts out data to sda pin on the rising edge of vsync clock. data format is an 8-bit byte followed by a null bit. most significant bit (msb) is transmitted first. every time when the ninth bit has been transmitted, the shift register will load a data byte from data buffer (reg#18h). after loading data to the shift register, the data buffer becomes empty and generates an int0 interrupt. so the program must write one data byte into reg#18 every nine vsync clocks. since the default values of data buffer(reg#22) and shift register are ffh, the sda pin outputs high level if no data had been written into data buffer after power on reset. when program finished initialization and set the ien_d bit to "1", the int0 will occur because the data buffer is empty. the int0 service routine should check the ddc2b bit is "0" and then writes the first edid data byte into data buffer. when the second int0 occurs, the int0 service routine writes the second edid data byte into data buffer and so on. shift register data buffer 1 1 0 0 0 0 0 address register address compare vsync internal data bus mux r/w msb addr enack sda scl start/stop detect handshake control start stop ddc2b i/o 1 2 18 3 9 10 19 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 sda vsync int0 ien_d load data to shift register
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 13 if a low level occurs on the scl pin in ddc1 state, the ddc interface will switch to ddc2b state immediately and set the ddc2b bit to "1". no interrupt will be generated. but, if there is no valid device address and it receives 128 v sync pulses while the scl is high level, it will go back to ddc1 state automatically. if it receives a valid device address, it will lock into ddc2b state and disregard vsync . in some case, program wants to go back ddc1 state, set rddc bit in reg#1ah and reset it again. this operation resets the ddc interface to the initial condition. when it is in ddc2b state, the vsync clock is disregarded and the communication protocol follows the ddc standard. the data format on sda pin is: s address r/w a d7,d6,...., d0 a d7,d6,...., d0 a p s : start condition. a falling edge occurs when scl is high level. p : stop condition. a rising edge occurs when scl is high level. a : acknowledge bit. ? 0 ? means acknowledge and ? 1 ? means non-acknowledge. address : 7-bit device address. r/ w : read/write control bit, "1" is read and "0" is write. d7 ,d6,...., d0 : data byte. the hardware operations in ddc2b state are : (1) start/stop detection when the start condition is detected, the ddc interface is enabled and set start bit to "1". when the stop condition is detected, the ddc interface is disabled, set stop bit to "1" and generate int0 interrupt. the start bit is cleared when the following data byte received. the stop bit is cleared after writing reg#19h. (2) address recognition it contains two device addresses in WT6018. one fixed address ( ? 1010000 ? ) is for edid reading and one programmable address (reg#19h) is for external control, such as auto alignment. if the address is equal to "1010000", set addr bit to "0". if the address is equal to the bit a6 to bit a0 (reg#19h), set addr bit to "1". if the address is not equal to anyone above, the ddc interface will not response acknowledge. the addr bit is updated when a new device address is received. (3) store r/w bit and decide the direction of sda pin the r/w bit on the sda pin will be stored in the rw bit. (4) acknowledge bit control/detection acknowledge bit control in receive direction : if enack=1 and address compare is true, response acknowledge (acknowledge bit ="0"). if enack=0 or address compare is false, response non-acknowledge (acknowledge bit ="1"). acknowledge bit detect in transmit direction : if the acknowledge bit is "1 " , the ddc interface will be disabled and release the sda pin. if the acknowledge bit is "0 " , the ddc interface keeps on communicating.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 14 (5) data bytes transmit/receive if the rw bit is "1", the shift register will load data from the data buffer (reg#18h) before the data byte is transmitted and shift out data to the sda pin before the rising edge of the scl clock. if the rw bit is "0", the shift register will shift in data on the rising edge of the scl clock and the whole data byte is latched to the data buffer(reg#18h). (6) handshaking procedure the handshaking is done on the byte level. the ddc interface will hold the scl pin low after the acknowledge bit automatically. the bus master will be forced to wait until the WT6018 is ready for the next byte transfer. to release the scl pin, write reg#19h will release clear the wait state. (7) interrupt int0 the ddc interface interrupt is enabled by setting the ien_d bit in the reg#1ah. interrupt int0 occurs when: - transmit buffer empty in ddc1 state. the int0 occurs when the shift register load data from data buffer. write reg#18h will clear the transmit buffer empty condition. - acknowledge is detected in ddc2b state. the int0 occurs on the falling edge of the scl clock after the acknowledge had been detected. the scl pin will be pulled low to force the bus master to wait until the service routine write reg#19h. - stop condition occurs in ddc2b mode address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0018h r/w ffh d7 d6 d5 d4 d3 d2 d1 d0 0019h r 40h ddc2b addr rw start stop -- -- -- 0019h w a0h a6 a5 a4 a3 a2 a1 a0 enack bit name bit value = ? 1 ? bit value = ? 0 ? ddc2b ddc2b state. ddc1 state. addr received address equals to the address in reg#19h(w). received address equals to ? 1010000 ? . rw received r/w bit is ? 1 ? . received r/w bit is ? 0 ? . start start condition is detected. no start condition is detected. stop stop condition is detected. no stop condition is detected. enack enable acknowledge. disable acknowledge. a6,a5, ? ., a0 7-bit slave address d7,d6, ? ., d0 data to be transmitted or received data.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 15 scl sda in 1 0 1 0 0 0 0 0 data byte data byte a a a out sda int0 shift register to data buffer ddc2b=1 addr=0 r/w=0 start=1 stop=0 ddc2b=1 addr=0 r/w=0 start=0 stop=0 ddc2b=1 addr=0 r/w=0 start=0 stop=1 ddc2b=1 addr=0 r/w=0 start=0 stop=0 pull low scl write reg#19h to release scl pull low scl pull low scl ddc2b state write timing scl sda in 1 1 1 0 0 0 0 0 data byte data byte a a n out sda int0 data buffer to shift reg ddc2b=1 addr=0 r/w=1 start=1 stop=0 ddc2b=1 addr=0 r/w=1 start=0 stop=0 ddc2b=1 addr=0 r/w=1 start=0 stop=1 pull low scl write reg#19h to release scl pull low scl ddc2b state read timing
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 16 interrupt control there are two interrupt sources : int0 and int1. int0 has the higher priority. interrupt vector : int0 : fffah (low byte) and fffbh (high byte). int1 : fffeh (low byte) and ffffh (high byte). int0 occurs when : (1) data buffer empty in the ddc1 mode (ddc="1" and ddc2b="0"). (2) acknowledge or stop condition is detected in the ddc2b mode (ddc="1" and ddc2b="0"). int1 occurs when : (1) a falling edge or a low level occurs on the /irq pin (ext="1"). (2) the timer is time out (tim="1"). (3) sync processor has a valid frequency (sync="1"). if h/v ="0 " , it is vertical frequency ready. if h/v ="1 " , it is horizontal frequency ready. int0 is cleared when : (1) writing the reg#18h in ddc1 state. (2) writing the reg#19h in ddc2b state. int1 is cleared when : (1) reading the reg#1ah if ext="1". (2) reading the reg#1bh if tim="1". (3) reading the reg#16h if sync="1". ien_x ien_t ien_s irq tout frdy int1 ien_d ddc d ck q q 4mhz int0
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 17 address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001ah w 00h ien_x ien_t ien_s ien_d edge rddc 0 0 001ah r 00h ext tim sync ddc irq tout frdy -- bit name bit value = ? 1 ? bit value = ? 0 ? ien_x enable /irq pin interrupt. disable /irq pin interrupt. ien_t enable timer interrupt. disable timer interrupt. ien_s enable sync processor interrupt. disable sync processor interrupt. ien_d enable ddc interface interrupt. disable ddc interface interrupt. edge /irq pin interrupt is edge trigger. /irq pin interrupt is level trigger. rddc reset ddc interface. it will always reset ddc interface if this bit keeps ? 1 ? . clear the reset of ddc interface. ext /irq pin interrupt occurs. no /irq pin interrupt. tim timer interrupt occurs. no timer interrupt. sync sync processor interrupt occurs. no sync processor interrupt. ddc ddc interface interrupt occurs. no ddc interface interrupt. irq /irq pin is low level /irq pin is high level tout timer is time-out. timer is not time-out. frdy h/v frequency counter is ready. the counter value is valid. h/v frequency counter is not ready. the counter value is invalid.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 18 timer it is a 8-bit down counter and clock frequency is 976.5625hz (period=1.024ms). the timer is started by writing a value into reg#1bh. when the timer counts down to zero, the timer stops, sets the tout bit and generates an int1 interrupt (if the ien_t bit is "1"). the tout bit will be cleared after reg#1bh is read. watch-dog timer the watch-dog timer is always enable after power is on. software must clear the watch-dog timer within every 524ms. if the watch-dog timer expired, it will cause the whole chip reset just like external reset. to clear the watch-dog timer, write any data to reg#1ch. address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001bh r/w -- tm7 tm6 tm5 tm4 tm3 tm2 tm1 tm0 001ch w -- wdt wdt wdt wdt wdt wdt wdt wdt bit name bit value tm7 to tm0 timer value (0 - 255) wdt write any value to this register will reset the watchdog timer.
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 19 a/d converter two 4-bit a/d converter inputs are shared with i/o port_c pc0 and pc1. use enad1 bit and enad0 bit to enable the corresponding a/d converter. the converted value is store in reg#20h. regardless of one a/d enabling or two a/d enabling ,the converted value is automatically updated at 2.048ms intervals. 4-bit data 0 0.75 4.02 address r/w initial bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0020h r -- ad13 ad12 ad11 ad10 ad03 ad02 ad01 ad00 0020h w 00h 0 0 0 0 0 0 enad1 enad0 bit name bit value = ? 1 ? bit value = ? 0 ? enad1 enable a/d converter 1. pin pc1 is the input of a/d converter 1. disable a/d converter 1. pin pc1 is i/o. enad0 enable a/d converter 0. pin pc0 is the input of a/d converter 0. disable a/d converter 0. pin pc0 is i/o. ad13, ? ,ad10 4-bit data of a/d converter 1. ad03, ? ,ad00 4-bit data of a/d converter 0. 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 volt
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 20 register map address r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000h r/w 80h da0 7 da0 6 da0 5 da0 4 da0 3 da0 2 da0 1 da0 0 0001h r/w 80h da1 7 da1 6 da1 5 da1 4 da1 3 da1 2 da1 1 da1 0 0002h r/w 80h da2 7 da2 6 da2 5 da2 4 da2 3 da2 2 da2 1 da2 0 0003h r/w 80h da3 7 da3 6 da3 5 da3 4 da3 3 da3 2 da3 1 da3 0 0004h r/w 80h da4 7 da4 6 da4 5 da4 4 da4 3 da4 2 da4 1 da4 0 0005h r/w 80h da5 7 da5 6 da5 5 da5 4 da5 3 da5 2 da5 1 da5 0 0006h r/w 80h da6 7 da6 6 da6 5 da6 4 da6 3 da6 2 da6 1 da6 0 0007h r/w 80h da7 7 da7 6 da7 5 da7 4 da7 3 da7 2 da7 1 da7 0 0008h r/w 80h da8 7 da8 6 da8 5 da8 4 da8 3 da8 2 da8 1 da8 0 0009h r/w 80h da9 7 da9 6 da9 5 da9 4 da9 3 da9 2 da9 1 da9 0 000ah r/w 80h da10 7 da10 6 da10 5 da10 4 da10 3 da10 2 da10 1 da10 0 000bh r/w 80h da11 7 da11 6 da11 5 da11 4 da11 3 da11 2 da11 1 da11 0 000ch r/w 80h da12 7 da12 6 da12 5 da12 4 da12 3 da12 2 da12 1 da12 0 000dh r/w 80h da13 7 da13 6 da13 5 da13 4 da13 3 da13 2 da13 1 da13 0 000eh reserved r x -- -- -- -- -- -- pd1r pd0r 000fh w 00h 0 0 0 enpd pd1oe pd0oe pd1w pd0w 0010h w 00h eho evo eda13 eda12 eda11 eda10 eda9 eda8 r x pa7r pa6r pa5r pa4r pa3r pa2r pa1r pa0r 0011h w ffh pa7w pa6w pa5w pa4w pa3w pa2w pa1w pa0w 0012h w 00h 0 pb6oe pb5oe pb4oe pb3oe pb2oe pb1oe pb0oe r x -- pb6r pb5r pb4r pb3r pb2r pb1r pb0r 0013h w ffh 1 pb6w pb5w pb4w pb3w pb2w pb1w pb0w 0014h w 00h pc7oe pc6oe pc5oe pc4oe pc3oe pc2oe pc1oe pc0oe r ffh pc7r pc6r pc5r pc4r pc3r pc2r pc1r pc0r 0015h w x pc7w pc6w pc5w pc4w pc3w pc2w pc1w pc0w r x f9 f8 f7 f6 f5 f4 f3 f2 0016h w 00h 0 0 enpat pat1 pat0 self h62k h48k r 00h h/v -- h_pol v_pol ovf2 ovf1 f1 f0 0017h w x 0 0 0 0 0 h+v hop vop 0018h r/w ffh d7 d6 d5 d4 d3 d2 d1 d0 r 40h ddc2b addr rw start stop -- -- -- 0019h w a0h a6 a5 a4 a3 a2 a1 a0 enack r 00h ext tim sync ddc irq tout frdy -- 001ah w 00h ien_x ien_t ien_s ien_d edge rddc 0 0 001bh r/w x tm7 tm6 tm5 tm4 tm3 tm2 tm1 tm0 001ch w x cwdt cwdt cwdt cwdt cwdt cwdt cwdt cwdt r x ad13 ad12 ad11 ad10 ad03 ad02 ad01 ad00 0020h w 00h 0 0 0 0 0 0 enad1 enad0 x : no default value. -- : no function. 0 : must write 0..
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 21 electrical characteristics absolute maximum ratings parameter min. max units dc supply voltage (vdd) -0.3 7.0 v input and output voltage with respect to ground all pins except da0 to da7 da0 to da7 -0.3 -0.3 vdd+0.3 11.5v v v storage temperature -65 150 o c ambient temperature with power applied -10 70 o c * note : stresses above those listed may cause permanent damage to the device. d.c. characteristics ( vdd=5.0v + 5% , ta=0 - 70 o c) symbol parameter condition min. typ. max. units v dd supply voltage 4.0 5 5.5 v v ih input high voltage all input pins (except hsync and vsync) 3.0 - vdd+ 0.3 v v il input low voltage all input pins (except hsync and vsync) -0.3 - 1.5 v v sih sync input high voltage hsync and vsync pin 2.0 - vdd+ 0.3 v v sil sync input low voltage hsync and vsync pin -0.3 - 0.8 v i oh = -100ua pa0-pa7 pins 3.5 - - v i oh = -6ma pb0-pb6, pc0-pc7, pd0, pd1, da8-da13, hso, vso and hso pins 3.5 - - v da0-da7 pins (external voltage) - - 10.5 v v oh output high voltage scl and sda pins (open drain) - - 5.5 v i ol = 5ma pa0-pa7, pb0-pb6, pd0-1, da0-da13, scl, sda, vso and hso pins - - 0.4 v v ol output low voltage i ol = 10ma pc0-pc7 pins - - 0.4 v i il input leakage current sda, scl, hsync and vsync pins ( v in = 0 to 5v) -10 - 10 ua r ph pull high resistance vin=0.8v pa0-pa7, pb0-pb6, pc0-pc7, /reset and /irq pins 16 22 28 kohm i dd operating current no load - 3 20 ma v reset reset voltage /reset pin 3.8 4.0 4.2 v
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 22 a.c. characteristics ( vdd=5.0v + 5%, fosc=8mhz, ta=0 - 70 o c) reset and irq timing symbol parameter min. typ. max. units t low,res /reset pin low pulse 250 - - ns t low,irq /irq low pulse (level trigger) 250 - - ns sync processor timing symbol parameter min. typ. max. units t high,sync hsync and vsync high time 250 - - ns t low,sync hsync and vsync low time 250 - - ns t fpw,hso self generated free-running hso pulse width - 2 - us t fpw,vso self generated free-running vso pulse width 4 x hso period t ipw,hso inserted hsync pulse width (composite sync input) - 2 - us ddc1 timing symbol parameter min. typ. max. units t vaa,ddc1 sda output valid from vsync rising edge 125 - 500 ns t mt mode transition time (ddc1 to ddc2b) - - 500 ns t high ,irq t low ,res reset irq t high ,sync t low ,sync hsync vsync t high ,sync t low ,sync vsync t vaa ,ddc1 t mt sda scl bit 0 (lsb) bit 7 (msb) null bit
WT6018 digital monitor controller ver. 1.41 jul-31-1998 weltrend semiconductor, inc. 23 ddc2b timing symbol parameter min. typ. max. units f scl scl input clock frequency 0 - 100 khz t bf bus free time 2 - - us t hd,start hold time for start condition 1 - - us t su,start set-up time for start condition 1 - - us t high,scl scl clock high time 1 - - us t low,scl scl clock low time 1 - - us hold time for data input 0 - - ns t hd,data hold time for data output 250 - - ns set-up time for data input 250 - - ns t su,data set-up time for data output 500 - - ns t rise scl and sda rise time - - 1 us t fall scl and sda fall time - - 300 ns t su,stop set-up time for stop condition 4 - - us t bf t su ,stop sda scl t rise t fall t low ,scl t high ,scl t su ,dat a t hd ,data t hd ,start t su ,start

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